The present invention relates generally to integrated circuit memory devices, and more particularly to the edge transition detection signal generated internal to an integrated circuit memory device.
Of concern in memory devices, such as asynchronous SRAM devices, that affects device performance and potentially device yield is the pulse width of an Edge Transition Detection (ETD) signal of the device. The ETD signal is often used in asynchronous SRAM devices as the internal clock of the device so that the device may operate in a synchronous manner internally. The ETD pulse controls such functions as the clocking of sense amplifiers of the device.
The duration of the ETD pulse is often of critical concern to the proper operation of the memory device. If the ETD pulse is too narrow, inadequate equilibration can occur, causing the device to slow or to fail, in the case of a device employing dynamic sense amplifiers. Conversely, if the ETD pulse is too wide, the device will be slower than it needs to be. The ETD pulse may need to be quite narrow, on the order of 1 to 3 nS, for instance. However, the ETD pulse is often subject to RC limitations as it is bussed around the device and this can degrade the ETD signal to an unacceptable level.
Due to the critical nature of the ETD signal, there is currently an unmet need in the art to be able to control the duration of an ETD pulse of a memory device as desired. Different ETD pulse widths would provide the advantage of being able to discover an optimal ETD pulse width with regard to device speed or yield.